vhdl_verification.vhd

Go to the documentation of this file.

-------------------------------------------------------------------------------
--! @file
--! @author Hipolito Guzman-Miranda
--! @brief Common datatypes and component declarations
-------------------------------------------------------------------------------

--! Use IEEE standard definitions library
library IEEE;
--! Use std_logic* signal types
use IEEE.STD_LOGIC_1164.all;

--! @brief Common datatypes and component declarations
--!
--! 
package vhdl_verification is

  --! @brief Output of datagen when \c valid='0'
  --!
  --! @detailed This data type has the same possible values that a \c std_logic
  --! can take, but adding the value
  --! \c keep, which means "maintain last valid value"
  type datagen_invalid_data is (
    keep,            -- Keep previous valid value
    uninitialized,   -- 'U'
    unknown,         -- 'X'
    zero,            -- '0'
    one,             -- '1'
    high_impedance,  -- 'Z'
    weak_unknown,    -- 'W'
    weak_zero,       -- 'L'
    weak_one,        -- 'H'
    dont_care);      -- '-'

  COMPONENT clkmanager
    generic (
      CLK_PERIOD       : time      := 10 ns;
      RST_ACTIVE_VALUE : std_logic := '0';
      RST_CYCLES       : integer   := 10
    );
    port (
      endsim : in  std_logic;
      clk    : out std_logic;
      rst    : out std_logic
    );
  END COMPONENT;

  COMPONENT datawrite
    generic (
      SIMULATION_LABEL         : string  := "datawrite";
      VERBOSE                  : boolean := false;
      DEBUG                    : boolean := false;
      OUTPUT_FILE              : string  := "./out/datawrite_test.txt";
      OUTPUT_NIBBLES           : integer := 2;
      DATA_WIDTH               : integer := 8
      );
    port (
      clk    : in std_logic;
      data   : in std_logic_vector (DATA_WIDTH-1 downto 0);
      valid  : in std_logic;
      endsim : in std_logic
      );
  END COMPONENT;

  COMPONENT datacompare
    generic (
      SIMULATION_LABEL         : string  := "datacompare";
      VERBOSE                  : boolean := false;
      DEBUG                    : boolean := false;
      GOLD_OUTPUT_FILE         : string  := "../test/datagen_test.txt";
      GOLD_OUTPUT_NIBBLES      : integer := 2;
      DATA_WIDTH               : integer := 8;
      ERROR_MARGIN             : integer := 0
      );
    port (
      clk    : in std_logic;
      data   : in std_logic_vector (DATA_WIDTH-1 downto 0);
      valid  : in std_logic;
      endsim : in std_logic
      );
  END COMPONENT;

  COMPONENT datagen
    generic (
      VERBOSE                  : boolean := false;
      DEBUG                    : boolean := false;
      STIMULI_FILE             : string  := "../test/datagen_test.txt";
      STIMULI_NIBBLES          : integer := 2;
      DATA_WIDTH               : integer := 8;
      THROUGHPUT               : integer := 0;
      INVALID_DATA             : datagen_invalid_data := unknown;
      CYCLES_AFTER_LAST_VECTOR : integer := 10
      );
    port (
      clk       : in std_logic;
      can_write : in std_logic;
      data      : out std_logic_vector (DATA_WIDTH-1 downto 0);
      valid     : out std_logic;
      endsim    : out std_logic
      );
  END COMPONENT;

  COMPONENT throughputchecker
    generic (
      SIMULATION_LABEL         : string  := "throughputchecker";
      DEBUG                    : boolean := false;
      THROUGHPUT               : integer := 0
      );
    PORT (
      clk : IN  std_logic;
      valid : IN  std_logic;
      endsim : IN  std_logic
      );
  END COMPONENT;

  component led_emu is
    generic (
      ACTIVE_VALUE : std_logic := '0'; --! Led polarity
      NUM_LEDS     : integer   := 4    --! How many leds are we emulating
      );
    port (
      led_input : in  std_logic_vector(NUM_LEDS-1 downto 0)  --! Connect here the signal that drives the leds
      );
  end component;

  component uart_emu is
    generic (
      OUTPUT_FILE  : string  := "uart.log"; --! File where received chars will be written
      VERBOSE      : boolean := false;      --! Log beginning and end of transactions, as well as individual bit values
      DATA_BITS    : integer := 8;          --! Number of data bits in the UART word
      PARITY       : string  := "none";     --! Can be either "even", "odd", or "none"
      BIT_DURATION : time    := 104 us;     --! Duration of each bit, depends on baudrate (it is actually 1 second / baudrate)
      STOP_BITS    : integer := 1           --! Can be either 1 or 2
    );
    port (
      uart_input   : in std_logic           --! Connect here the TX signal from your design
    );
  end component;

  component keypad_emu is
    generic (
      VERBOSE        : boolean := false
    );
    port (
      keypad_rows    : out  std_logic_vector(3 downto 0); --! This is the signal that must be read from the keypad
      keypad_columns : in   std_logic_vector(3 downto 0); --! Connect here the signal that drives the keypad
      pressed_keys   : in   std_logic_vector(15 downto 0) --! One bit for each key. Set to '1' to emulate key press, set to '0' to emulate key release
    );
  end component;

function slv2hexstring (data: std_logic_vector) return string;
  function slv2string (a : std_logic_vector) return string;
  function padstring (a: string) return string;
  function xor_reduce (a: std_logic_vector) return std_logic;
  function xnor_reduce (a: std_logic_vector) return std_logic;

end vhdl_verification;

package body vhdl_verification is

  -- Convert std_logic_vector (slv) to hexadecimal string
  function slv2hexstring(data : std_logic_vector) return string is
    variable binstr : string (1 to ((data'length+3)/4)*4);
    variable hexstr : string (1 to (data'length+3)/4);
  begin
    binstr := padstring(slv2string(data));
    for i in 1 to hexstr'length loop
        case binstr(((i-1)*4)+1 to ((i-1)*4)+4) is
            when "0000" => hexstr(i) := '0';
            when "0001" => hexstr(i) := '1';
            when "0010" => hexstr(i) := '2';
            when "0011" => hexstr(i) := '3';
            when "0100" => hexstr(i) := '4';
            when "0101" => hexstr(i) := '5';
            when "0110" => hexstr(i) := '6';
            when "0111" => hexstr(i) := '7';
            when "1000" => hexstr(i) := '8';
            when "1001" => hexstr(i) := '9';
            when "1010" => hexstr(i) := 'A';
            when "1011" => hexstr(i) := 'B';
            when "1100" => hexstr(i) := 'C';
            when "1101" => hexstr(i) := 'D';
            when "1110" => hexstr(i) := 'E';
            when "1111" => hexstr(i) := 'F';
            when others => hexstr(i) := 'X';
        end case;
    end loop;
    return hexstr;
  end slv2hexstring;

  -- Convert std_logic_vector to string
  function slv2string ( a: std_logic_vector) return string is
      variable b : string (1 to a'length) := (others => NUL);
      variable stri : integer := 1;
  begin
          for i in a'range loop
              b(stri) := std_logic'image(a((i)))(2);
              stri := stri + 1;
          end loop;
      return b;
  end function;

  -- Pad string to nearest multiple of 4
  function padstring (a: string) return string is
      variable b : string (1 to ((a'length+3)/4)*4);
      variable padlen : integer := b'length - a'length;
  begin
      for i in 1 to padlen loop
        b(i) := '0';
      end loop;
      for i in padlen+1 to b'length loop
        b(i+padlen) := a(i);
      end loop;
      return b;
  end function;

  -- Perform an xor reduction
  function xor_reduce (a: std_logic_vector) return std_logic is
      variable ret: std_logic;
  begin
      ret := '0';
      for i in a'range loop
          ret := ret xor a(i);
      end loop;
      return ret;
  end function;

  -- Perform an xnor reduction
  function xnor_reduce (a: std_logic_vector) return std_logic is
  begin
      return not xor_reduce(a);
  end function;

end vhdl_verification;