throughputchecker Entity Reference

Checks that data is valid with a specific data rate. More...

Detailed Description

Checks that data is valid with a specific data rate.

Checks that valid is active once each THROUGHPUT cycles. Assumes valid is active high. Also reports the total number of valid data seen when endsim is asserted. Note that this entity does not need to know the actual value of the data, only the value of the accompanying valid signal

Definition at line 27 of file throughputchecker.vhd.

Entities
compare_with_expected	architecture
	Architecture compares input data rate with expected data rate. More...

Libraries
ieee
	Use IEEE standard definitions library;.

Use Clauses
std_logic_1164
	Use std_logic* signal types.
numeric_std
	Allows use of arithmetical operations between integers and vectors.
textio
	Allows writing strings to lines and lines to files.
std_logic_textio
	Allows writing std_logic_vector(s) to line(s) in BIN, HEX, OCT and reading BIN, HEX, OCT vector(s) from line(s)
txt_util	Package <txt_util>
	For print() function.

Generics
SIMULATION_LABEL	string := " throughputchecker "
	To separate messages from different instances in simulation.
DEBUG	boolean := false
	Print debug info (developers)
THROUGHPUT	integer := 0
	Wait cycles between valid data.

Ports
clk	in std_logic
	Input data is aligned to this clock.
valid	in std_logic
	Active high, indicates data is valid.
endsim	in std_logic
	Active high, tells the process that last data from datagen was sent.

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The documentation for this class was generated from the following file:

• src/throughputchecker.vhd