compare_with_expected Architecture Reference

Architecture compares input data rate with expected data rate. More...

Detailed Description

Architecture compares input data rate with expected data rate.

After first valid data is seen, internally counts from 0 to THROUGHPUT - 1 and checks if valid is '1' when expected

Definition at line 44 of file throughputchecker.vhd.

Processes
expecting_valid	( )
	Computes expected value for valid and reports an error if actual value is different.

Signals
cycle_count	integer := THROUGHPUT - 1
	Cycles until next expected data.
valid_count	integer := 0
	Valid data seen.
expected_valid	std_logic := ' 1 '
	Expected value for 'valid'.

Member Function Documentation

expecting_valid()

expecting_valid ( )

Process

Computes expected value for valid and reports an error if actual value is different.

Manages this by waiting for first valid and keeping an internal count. When endsim is asserted, reports total valid data seen

Definition at line 60 of file throughputchecker.vhd.

  begin

    -- wait until the first valid to start counting down
    while (valid /= '1') loop
      wait until rising_edge(clk);
    end loop;

    while (endsim /= '1') loop
    
      assert (valid = '0' OR valid = '1')
        report "throughputchecker(" & SIMULATION_LABEL & "): invalid value for valid, should only have '0' or '1'! (got '" & std_logic'image(valid) & "')"
        severity failure;    
    
      if (valid /= expected_valid) then
        if (valid = '1' and expected_valid = '0') then
          report "throughputchecker(" & SIMULATION_LABEL & "): ERROR: data valid " & integer'image(cycle_count + 1) & " cycles before expected" severity error;
        end if;
      end if;
      
      if (valid = '1') then
        valid_count <= valid_count + 1;
        print (DEBUG, "seen valid, valid_count: " & integer'image(valid_count + 1));
      end if;

      if (cycle_count = 0) then
        cycle_count <= THROUGHPUT - 1;
        expected_valid <= '1';
      else
        cycle_count <= cycle_count - 1;
        expected_valid <= '0';
      end if;

      -- Wait for next rising edge of clk
      -- if endsim is asserted, do not wait for the clk edge, because it will never come
      wait until rising_edge(clk) or (endsim = '1');
      
    end loop;
  
    report "throughputchecker(" & SIMULATION_LABEL & "): test end. valid_count: " & integer'image(valid_count) severity note;
    
    wait;
    
  end process;

---

The documentation for this class was generated from the following file:

• src/throughputchecker.vhd

---

Generated on Wed Dec 16 2020 18:16:22 for VHDL-verification by   1.8.13