VHDL-verification
Package to ease directed testing of HDL entities
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Allows for text output in simulation. More...
Allows for text output in simulation.
Definition at line 12 of file txt_util.vhd.
Functions | |
character | chr ( sl: in std_logic ) |
converts std_logic into a character | |
character | ascii ( int: in integer ) |
converts an 8-bit integer into a printable character | |
string | str ( sl: in std_logic ) |
converts std_logic into a string (1 to 1) | |
string | str ( slv: in std_logic_vector ) |
converts std_logic_vector into a string (binary base) | |
string | str ( b: in boolean ) |
converts boolean into a string | |
character | chr ( int: in integer ) |
converts an integer into a single character | |
string | str ( int: in integer , base: in integer ) |
converts integer into string using specified base | |
string | str ( int: in integer ) |
converts integer to string, using base 10 | |
string | hstr ( slv: in std_logic_vector ) |
convert std_logic_vector into a string in hex format | |
character | to_upper ( c: in character ) |
convert a character to upper case | |
character | to_lower ( c: in character ) |
convert a character to lower case | |
string | to_upper ( s: in string ) |
convert a string to upper case | |
string | to_lower ( s: in string ) |
convert a string to lower case | |
std_logic | to_std_logic ( c: in character ) |
converts a character into std_logic | |
std_logic_vector | to_std_logic_vector ( s: in string ) |
converts a string into std_logic_vector |
Procedures | |
print( text: string ) | |
prints a message to the screen | |
print( active: boolean , text: string ) | |
prints the message when active | |
str_read( res_string: out string ) | |
read variable length string from input file | |
print( new_string: in string ) | |
print string to a file and start new line | |
print( char: in character ) | |
print character to a file and start new line |
Libraries | |
ieee |
Use Clauses | |
std_logic_1164 | |
textio |