datacompare Entity Reference

Compares input data with values in file and reports errors. More...

Detailed Description

Compares input data with values in file and reports errors.

Reads file at GOLD_OUTPUT_FILE, expecting GOLD_OUTPUT_NIBBLES chars in each line. Data is expected in hex format: 4 bits per character (nibble). Reads input data and internally reorders it so it can compare accumulated data with a complete line in GOLD_OUTPUT_FILE outputs it with a width of DATA_WIDTH bits. data is only sampled when valid is active. If VERBOSE is true, will report both correct (OK) data with erroneous (ERROR) data

Definition at line 31 of file datacompare.vhd.

Entities
data_comparison	architecture
	Architecture accumulates input data in a vector and compares with contents of file lines. More...

Libraries
ieee
	Use IEEE standard definitions library.

Use Clauses
std_logic_1164
	Use std_logic* signal types.
numeric_std
	Allows use of arithmetical operations between integers and vectors.
textio
std_logic_textio
txt_util	Package <txt_util>
vhdl_verification	Package <vhdl_verification>

Generics
SIMULATION_LABEL	string := " datacompare "
	Allow to separate messages from different instances in SIMULATION.
VERBOSE	boolean := false
	Report correct data and not only erroneous data.
DEBUG	boolean := false
	Print debug info (developers only)
GOLD_OUTPUT_FILE	string := " ../test/datacompare_test.txt "
	File where data is stored.
GOLD_OUTPUT_NIBBLES	integer := 2
	Maximum hex chars for each output data.
DATA_WIDTH	integer := 8
	Width of inout data.
ERROR_MARGIN	integer := 0
	Comparison is ok if data differs by this value or less.

Ports
clk	in std_logic
	Expects input data aligned to this clock.
data	in std_logic_vector ( DATA_WIDTH - 1 downto 0 )
	Data to compare with data in file.
valid	in std_logic
	Active high, indicates data is valid.
endsim	in std_logic
	Active high, tells the process to close its open files.

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The documentation for this class was generated from the following file:

• src/datacompare.vhd