data_comparison Architecture Reference

Architecture accumulates input data in a vector and compares with contents of file lines. More...

Detailed Description

Architecture accumulates input data in a vector and compares with contents of file lines.

Definition at line 50 of file datacompare.vhd.

Processes
datacompare_read	( )
	Reads the file line by line, accumulates data and compares.

Constants
NUM_CHUNKS	integer := 4 * GOLD_OUTPUT_NIBBLES / DATA_WIDTH
	Each line in output file equals to NUM_CHUNKS data of DATA_WIDTH.

Signals
received_data	integer := 0

Shared Variables
gold_file_isopen	shared boolean := := false

Files
gold_file_pointer	text
	Define this outside the process so we can check endfile(gold_file_pointer) in a concurrent assertion.

Member Function Documentation

datacompare_read()

datacompare_read ( )

Process

Reads the file line by line, accumulates data and compares.

Also reports errors and checks for unexpected conditions

Definition at line 86 of file datacompare.vhd.

    
    --file gold_file_pointer    : text; 
    variable current_line     : line;
    variable expected_data    : std_logic_vector (GOLD_OUTPUT_NIBBLES*4-1 downto 0); -- Data read from file
    variable current_data     : std_logic_vector (GOLD_OUTPUT_NIBBLES*4-1 downto 0); -- Data read from input
    variable chunk_idx        : integer range 0 to NUM_CHUNKS := 0;               -- Points to current data chunk in line
    variable error_count      : integer := 0;                                     -- Store differences between received and expected data
    variable correct_count    : integer := 0;                                     -- Store number of correct data

  begin
   
    print ("datacompare(" & SIMULATION_LABEL & "): NUM_CHUNKS: " & integer'image(NUM_CHUNKS));
    print ("datacompare(" & SIMULATION_LABEL & "): opening gold_output file " & GOLD_OUTPUT_FILE);
    file_open(gold_file_pointer, GOLD_OUTPUT_FILE, READ_MODE);
    gold_file_isopen := true;

    while (not endfile(gold_file_pointer)) loop  
    
      print (DEBUG, "datacompare(" & SIMULATION_LABEL & "): reading line");
      readline (gold_file_pointer, current_line);         -- Read the whole line from the file

      -- Before converting line to std_logic_vector, assert that number of nibbles read matches expected
      -- Since a line is a pointer (technically an "access", in VHDL) to a string,
      -- current_line.all is a string, so check its length
      assert current_line.all'LENGTH = GOLD_OUTPUT_NIBBLES
        report "datagen: unexpected number of nibbles in gold output file, got " & integer'image(current_line.all'LENGTH) & ", expected " & integer'image(GOLD_OUTPUT_NIBBLES)
        severity failure;

      hread (current_line, expected_data);        -- Interpret the line as hex data and put it in a std_logic_vector
      
      while ((chunk_idx < NUM_CHUNKS)) loop
        wait until rising_edge(clk);
        if (valid = '1') then
          print (DEBUG,  "datacompare(" & SIMULATION_LABEL & "): chunk_idx: " & integer'image(chunk_idx));
          current_data(DATA_WIDTH*(chunk_idx+1)-1 downto DATA_WIDTH*chunk_idx) := data; -- Put input data in the correct chunk           
          chunk_idx := chunk_idx + 1;
          received_data <= received_data + 1;
        end if;
      end loop;

      if (abs(signed(current_data) - signed(expected_data)) > ERROR_MARGIN) then
        report "datacompare(" & SIMULATION_LABEL & "): ERROR: received " & slv2hexstring (current_data) & ", expecting " & slv2hexstring (expected_data)
          severity error;
        error_count := error_count + 1;
      else
        if (VERBOSE = true) then
          report "datacompare(" & SIMULATION_LABEL & "): data OK, received " & slv2hexstring (current_data) & ", expecting " & slv2hexstring (expected_data) severity note;
        end if;
        correct_count := correct_count + 1;
      end if;
      
      chunk_idx := 0;
      
    end loop;
    
    file_close(gold_file_pointer);
    gold_file_isopen := false;
     
    wait until (falling_edge(clk) or (endsim='1'));
    
    print (VERBOSE,  "datacompare(" & SIMULATION_LABEL & "): " & integer'image(received_data) & " data received");
    print (VERBOSE,  "datacompare(" & SIMULATION_LABEL & "): No more data in output file, closing it");
 
    wait until endsim='1';

    assert correct_count > 0
      report "datacompare(" & SIMULATION_LABEL & "): simulation finished but correct data is not > 0. correct data: " & integer'image(correct_count) severity failure;

    report "datacompare(" & SIMULATION_LABEL & "): test end, errors: " & integer'image(error_count) & " correct data: " & integer'image(correct_count) severity note;

    wait;
    
  end process datacompare_read;

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The documentation for this class was generated from the following file:

• src/datacompare.vhd

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Generated on Wed Dec 16 2020 18:16:22 for VHDL-verification by   1.8.13