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VHDL-verification
Package to ease directed testing of HDL entities
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Common datatypes and component declarations. More...
Common datatypes and component declarations.
Definition at line 15 of file vhdl_verification.vhd.
Functions | |
| string | slv2hexstring ( data: in std_logic_vector ) |
| One bit for each key. Set to '1' to emulate key press, set to '0' to emulate key release. | |
| string | slv2string ( a: in std_logic_vector ) |
| string | padstring ( a: in string ) |
| std_logic | xor_reduce ( a: in std_logic_vector ) |
| std_logic | xnor_reduce ( a: in std_logic_vector ) |
Libraries | |
| IEEE | |
| Use IEEE standard definitions library. | |
Use Clauses | |
| STD_LOGIC_1164 | |
| Use std_logic* signal types. | |
Components | |
| clkmanager | <Entity clkmanager> |
| datawrite | <Entity datawrite> |
| datacompare | <Entity datacompare> |
| datagen | <Entity datagen> |
| throughputchecker | <Entity throughputchecker> |
| led_emu | <Entity led_emu> |
| Led polarity. | |
| uart_emu | <Entity uart_emu> |
| Connect here the signal that drives the leds. | |
| keypad_emu | <Entity keypad_emu> |
| Connect here the TX signal from your design. | |
Types | |
| datagen_invalid_data | ( keep , uninitialized , unknown , zero , one , high_impedance , weak_unknown , weak_zero , weak_one , dont_care ) |
Output of datagen when valid='0'. | |
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Type |
Output of datagen when valid='0'.
This data type has the same possible values that a std_logic can take, but adding the value keep, which means "maintain last valid value"
Definition at line 22 of file vhdl_verification.vhd.
1.8.13