datagen Entity Reference

Reads stimuli from file and outputs it with specified format. More...

Detailed Description

Reads stimuli from file and outputs it with specified format.

Reads file at STIMULI_FILE, expecting STIMULI_NIBBLES chars in each line. Data is expected in hex format: 4 bits per character (nibble). Reads the data and outputs it with a width of DATA_WIDTH bits, asserting valid='1' when a new data is available. Outputs a new data each THROUGHPUT cycles, unless can_write='0'. When valid='0', output bits are set to INVALID_DATA. After last data in STIMULI_FILE has been output, waits for CYCLES_AFTER_LAST_VECTOR clk cycles and afterwards asserts endsim.

Definition at line 31 of file datagen.vhd.

Entities
data_generation	architecture
	Architecture reads file lines and slices it into chunks of size DATA_WIDTH. More...

Libraries
ieee
	Use IEEE standard definitions library.

Use Clauses
std_logic_1164
	Use std_logic* signal types.
numeric_std
	Allows use of arithmetical operations between integers and vectors.
textio
	Allows writing strings to lines and lines to files.
std_logic_textio
	Allows writing std_logic_vector(s) to line(s) in BIN, HEX, OCT and reading BIN, HEX, OCT vector(s) from line(s)
txt_util	Package <txt_util>
	For print() function.
vhdl_verification	Package <vhdl_verification>
	For datagen_invalid_data definition.

Generics
VERBOSE	boolean := false
	Print more internal details.
DEBUG	boolean := false
	Print debug info (developers only)
STIMULI_FILE	string := " ../test/datagen_test.txt "
	File where data is stored.
STIMULI_NIBBLES	integer := 2
	Maximum hex chars for each input data.
DATA_WIDTH	integer := 8
	Width of generated data.
THROUGHPUT	integer := 0
	Output 1 valid data each THROUGHPUT cycles.
INVALID_DATA	datagen_invalid_data := unknown
	Output value when data is not valid.
CYCLES_AFTER_LAST_VECTOR	integer := 10
	Number of cycles between last data and assertion of endsim.

Ports
clk	in std_logic
	Align generated data to this clock.
can_write	in std_logic
	Active high, tells datagen it can assert valid. Use for control-flow.
data	out std_logic_vector ( DATA_WIDTH - 1 downto 0 )
	Generated data.
valid	out std_logic
	Active high, indicates data is valid.
endsim	out std_logic
	Active high, tells the other simulation processes to close their open files.

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The documentation for this class was generated from the following file:

• src/datagen.vhd