VHDL-verification
Package to ease directed testing of HDL entities
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Architecture reads file lines and slices it into chunks of size DATA_WIDTH
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Architecture reads file lines and slices it into chunks of size DATA_WIDTH
.
Definition at line 52 of file datagen.vhd.
Processes | |
datagen_read | ( ) |
Manage data generation from data in STIMULI_FILE. | |
invalid_data_behavior | ( last_valid_data ) |
Cycles to wait before outputting next data. |
Constants | |
NUM_CHUNKS | integer := 4 * STIMULI_NIBBLES / DATA_WIDTH |
Each line in input file equals to NUM_CHUNK data of DATA_WIDTH. |
Signals | |
cycle_count | integer := 0 |
Cycle counter. | |
sent_data | integer := 0 |
Data sent to output. | |
last_valid_data | std_logic_vector ( DATA_WIDTH - 1 downto 0 ) |
Last data when valid was '1'. | |
invalid_output | std_logic_vector ( DATA_WIDTH - 1 downto 0 ) |
Output value when data_valid = '0'. |