VHDL-verification
Package to ease directed testing of HDL entities
Functions
vhdl_verification Package Body Reference

Detailed Description

Definition at line 158 of file vhdl_verification.vhd.

Package >> vhdl_verification

Functions

string   slv2hexstring ( data: in std_logic_vector )
string   slv2string ( a: in std_logic_vector )
string   padstring ( a: in string )
std_logic   xor_reduce ( a: in std_logic_vector )
std_logic   xnor_reduce ( a: in std_logic_vector )
The documentation for this class was generated from the following file:
Generated on Wed Dec 16 2020 18:16:22 for VHDL-verification by   doxygen 1.8.13