clkmanager Entity Reference

Generates a clock and reset for simulation purposes. More...

Detailed Description

Generates a clock and reset for simulation purposes.

Generates a clock, clk, with period CLK_PERIOD, and also a reset pulse, which takes the value RST_ACTIVE_VALUE during RST_CYCLES (of the generated clock), and after that time switches to the opposite value

Definition at line 17 of file clkmanager.vhd.

Entities
two_simulation_processes	architecture
	Architecture is based on two different non-synthesizable processes to manage clk and rst. More...

Libraries
ieee
	Use IEEE standard definitions library.

Use Clauses
std_logic_1164
	Use std_logic* signal types.

Generics
CLK_PERIOD	time := 10 ns
	Period of generated clock.
RST_ACTIVE_VALUE	std_logic := ' 0 '
	Reset polarity.
RST_CYCLES	integer := 10
	Number of cycles that reset will be asserted at the beginning of the simulation.

Ports
endsim	in std_logic
	clk stops changing when endsim='1', which effectively stops the simulation
clk	out std_logic
	Generated clock.
rst	out std_logic
	Generated reset.

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The documentation for this class was generated from the following file:

• src/clkmanager.vhd