two_simulation_processes Architecture Reference

Architecture is based on two different non-synthesizable processes to manage clk and rst. More...

Detailed Description

Architecture is based on two different non-synthesizable processes to manage clk and rst.

A process is dedicated to toggle clk while endsim is not '1', and another one manages rst

Definition at line 33 of file clkmanager.vhd.

Processes
clk_process	( )
	Manage clk.
rst_process	( )
	Manage reset.

Member Function Documentation

clk_process()

clk_process ( )

Process

Manage clk.

To stop the simulation without a failure message, stop toggling the clk when endsim = '1',

Definition at line 56 of file clkmanager.vhd.

  begin
    if(endsim /= '1') then
      clk <= '0';
      wait for CLK_PERIOD/2;
      clk <= '1';
      wait for CLK_PERIOD/2;
    else
      wait;
    end if;
  end process;

rst_process()

rst_process ( )

Process

Manage reset.

Sets rst to RST_ACTIVE_VALUE for CLK_PERIOD*RST_CYCLES and toggles it to NOT RST_ACTIVE_VALUE after that time

Definition at line 72 of file clkmanager.vhd.

  begin     
    rst <= RST_ACTIVE_VALUE;
    wait for CLK_PERIOD*RST_CYCLES;
    rst <= NOT RST_ACTIVE_VALUE;
    wait;
  end process;

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The documentation for this class was generated from the following file:

• src/clkmanager.vhd

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Generated on Wed Dec 16 2020 18:16:22 for VHDL-verification by   1.8.13