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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| VHDL para sÃntesis.pdf | 2021-09-06 18:45 | 226K | |
| Tema9_FPGA2.pdf | 2021-09-06 18:50 | 5.5M | |
| Tema8_FPGA1.pdf | 2021-09-06 18:51 | 4.1M | |
| Tema7_diseno.pdf | 2021-09-06 18:46 | 2.8M | |
| Tema6_Registros.pdf | 2021-09-06 18:46 | 1.8M | |
| Tema5_Combincionales..> | 2021-09-06 18:46 | 733K | |
| Tema4_Modelo.pdf | 2021-09-06 18:46 | 1.7M | |
| Tema3_ReglasII.pdf | 2021-09-06 18:46 | 2.4M | |
| Tema2_procesoCMOS.pdf | 2021-09-06 18:46 | 2.4M | |
| Tema1_intrmicroelect..> | 2021-09-06 18:51 | 3.9M | |
| PracticaFPGA2.pdf | 2021-09-06 18:45 | 160K | |
| PracticaFPGA1.pdf | 2021-09-06 18:46 | 126K | |
| Guia_rapida_ISE_LX9_..> | 2021-09-06 18:49 | 19M | |
| ArquitecturaInternaF..> | 2021-09-06 18:46 | 774K | |