VHDL-verification
Package to ease directed testing of HDL entities
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Checks that a specific valid signal is active with expected data rate. More...
Go to the source code of this file.
Checks that a specific valid signal is active with expected data rate.
Definition in file throughputchecker.vhd.
Entities | |
throughputchecker | entity |
Checks that data is valid with a specific data rate. More... | |
compare_with_expected | architecture |
Architecture compares input data rate with expected data rate. More... | |