VHDL-verification
Package to ease directed testing of HDL entities
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Generates reset and clock for simulation purposes. More...
Go to the source code of this file.
Generates reset and clock for simulation purposes.
Definition in file clkmanager.vhd.
Entities | |
clkmanager | entity |
Generates a clock and reset for simulation purposes. More... | |
two_simulation_processes | architecture |
Architecture is based on two different non-synthesizable processes to manage clk and rst . More... | |