VHDL-verification
Package to ease directed testing of HDL entities
Entities
clkmanager.vhd File Reference

Generates reset and clock for simulation purposes. More...

Go to the source code of this file.

Detailed Description

Generates reset and clock for simulation purposes.

Author
Hipolito Guzman-Miranda

Definition in file clkmanager.vhd.

Entities

clkmanager  entity
 Generates a clock and reset for simulation purposes. More...
 
two_simulation_processes  architecture
 Architecture is based on two different non-synthesizable processes to manage clk and rst. More...