VHDL-verification
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pack_lines_and_write Architecture Reference

Architecture accumulates input data in a vector which will be written to the output file. More...

Detailed Description

Architecture accumulates input data in a vector which will be written to the output file.

Definition at line 47 of file datawrite.vhd.

Processes

datawrite_read  ( )
 Accumulates data to form a line, when line is complete it gets written to the output file.

Constants

NUM_CHUNKS  integer := 4 * OUTPUT_NIBBLES / DATA_WIDTH
 Each line in output file equals to NUM_CHUNKS data of DATA_WIDTH.

Signals

received_data  integer := 0

Member Function Documentation

◆ datawrite_read()

datawrite_read ( )
Process

Accumulates data to form a line, when line is complete it gets written to the output file.

Also reports errors and checks for unexpected conditions

Definition at line 74 of file datawrite.vhd.

datawrite_read : process
74 
75  file file_pointer : text;
76  variable current_line : line;
77  variable expected_data : std_logic_vector (OUTPUT_NIBBLES*4-1 downto 0); -- Data read from file
78  variable current_data : std_logic_vector (OUTPUT_NIBBLES*4-1 downto 0); -- Data read from input
79  variable chunk_idx : integer range 0 to NUM_CHUNKS := 0; -- Points to current data chunk in line
80  variable error_count : integer := 0; -- Store differences between received and expected data
81  variable correct_count : integer := 0; -- Store number of correct data
82 
83  begin
84 
85  print ("datawrite(" & SIMULATION_LABEL & "): NUM_CHUNKS: " & integer'image(NUM_CHUNKS));
86  print ("datawrite(" & SIMULATION_LABEL & "): opening output file " & OUTPUT_FILE);
87  file_open(file_pointer, OUTPUT_FILE, WRITE_MODE);
88 
89  while (endsim /= '1') loop
90 
91  print (DEBUG, "datawrite(" & SIMULATION_LABEL & "): composing line");
92 
93  while (chunk_idx < NUM_CHUNKS and endsim /= '1') loop
94  wait until (rising_edge(clk) or endsim = '1');
95  if (valid = '1') then
96  print (DEBUG, "datawrite(" & SIMULATION_LABEL & "): chunk_idx: " & integer'image(chunk_idx));
97  current_data(DATA_WIDTH*(chunk_idx+1)-1 downto DATA_WIDTH*chunk_idx) := data; -- Put input data in the correct chunk
98  chunk_idx := chunk_idx + 1;
99  received_data <= received_data + 1;
100  end if;
101  end loop;
102 
103  if (chunk_idx /= NUM_CHUNKS and chunk_idx /= 0) then
104  print ("datawrite(" & SIMULATION_LABEL & "): warning: endsim received whilst line not completed. (chunk_idx = " & integer'image(chunk_idx) & "). Some data may be lost" );
105  end if;
106 
107  -- Avoid writing twice the last line
108  if (endsim /= '1') then
109  print (DEBUG, "datawrite(" & SIMULATION_LABEL & "): writing line");
110  hwrite(current_line, current_data);
111  writeline(file_pointer, current_line);
112  end if;
113 
114  current_data := (others => 'U');
115  chunk_idx := 0;
116 
117  end loop;
118 
119  print (VERBOSE, "datawrite(" & SIMULATION_LABEL & "): " & integer'image(received_data) & " data received");
120  print (VERBOSE, "datawrite(" & SIMULATION_LABEL & "): Closing output file");
121 
122  file_close(file_pointer);
123 
124  wait;
125 
126  end process datawrite_read;
127 
in datastd_logic_vector( DATA_WIDTH- 1 downto 0)
Data to write to file.
Definition: datawrite.vhd:40
DATA_WIDTHinteger := 8
Width of input data.
Definition: datawrite.vhd:37
SIMULATION_LABELstring := "datawrite"
Allow to separate messages from different instances in SIMULATION.
Definition: datawrite.vhd:31
OUTPUT_FILEstring := "./output/datawrite_test.txt"
File where data will be stored.
Definition: datawrite.vhd:34
in validstd_logic
Active high, indicates data is valid.
Definition: datawrite.vhd:41
VERBOSEboolean := false
Print more internal details.
Definition: datawrite.vhd:32
in endsimstd_logic
Active high, tells the process to close its open files.
Definition: datawrite.vhd:43
integer := 4* OUTPUT_NIBBLES/ DATA_WIDTH NUM_CHUNKS
Each line in output file equals to NUM_CHUNKS data of DATA_WIDTH.
Definition: datawrite.vhd:49
OUTPUT_NIBBLESinteger := 2
Hex chars on each output line.
Definition: datawrite.vhd:35
in clkstd_logic
Will sample input on rising_edge of this clock.
Definition: datawrite.vhd:39
DEBUGboolean := false
Print debug info (developers only)
Definition: datawrite.vhd:33

The documentation for this class was generated from the following file: