library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_verification.all;

entity tb_throughputchecker is
end tb_throughputchecker;

architecture behavior of tb_throughputchecker is

  constant THROUGHPUT : integer := 10;

  --Inputs
  signal clk    : std_logic := '0';
  signal valid  : std_logic := '0';
  signal endsim : std_logic := '0';

  -- Clock period definitions
  constant clk_period : time := 10 ns;

  signal count : integer range 0 to THROUGHPUT - 1;

begin

  -- Instantiate the Unit Under Test (UUT)
  uut : throughputchecker
    generic map (
      SIMULATION_LABEL => "throughputchecker",
      THROUGHPUT       => THROUGHPUT
      )
    port map (
      clk    => clk,
      valid  => valid,
      endsim => endsim
      );

  -- To stop the simulation without a failure message,
  -- stop the clock when endsim = '1',
  clk_process : process
  begin
    if(endsim /= '1') then
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
    else
      wait;
    end if;
  end process;

  -- Stimulus process
  stim_proc : process
  begin
    wait until rising_edge(clk);
    if (count = 0) then
      count <= THROUGHPUT - 1;
      valid <= '1';
    else
      count <= count - 1;
      valid <= '0';
    end if;
  end process;

  endsim <= '0', '1' after 100*clk_period;

end;