library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_verification.all;

entity tb_led_emu is
end tb_led_emu;

architecture behavior of tb_led_emu is

  constant ACTIVE_VALUE : std_logic := '1';
  constant NUM_LEDS     : integer   := 4;

  --Inputs
  signal led_input      : std_logic_vector(NUM_LEDS-1 downto 0);

  -- Clock period and signal definition
  -- (we don't actually have a clock in this testbench, but it's nice to have
  -- some time magnitude, to wait for multiples of it)
  constant clk_period   : time      := 10 ns;
  signal clk            : std_logic := '0';

  -- Simulation control
  constant MAX_CYCLES   : integer   := 64;
  signal num_cycles     : integer   := 0;

begin

  -- Instantiate the Unit Under Test (UUT)
  uut : led_emu
    generic map (
      ACTIVE_VALUE => ACTIVE_VALUE,
      NUM_LEDS     => NUM_LEDS
      )
    port map (
      led_input    => led_input
      );

  -- To stop the simulation without a failure message,
  -- stop the clock when we reach the desired number of cycles
  clk_process : process
  begin
    if(num_cycles < MAX_CYCLES) then
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
      num_cycles <= num_cycles + 1;
    else
      report "Ending simulation";
      wait;
    end if;
  end process;

  -- Stimulus process
  stim_proc : process
  begin
    wait for clk_period*10;
    led_input <= "0000";
    for i in 0 to 3 loop
        led_input <= (others => NOT ACTIVE_VALUE);
        led_input(i) <= ACTIVE_VALUE;
        wait for clk_period;
    end loop;
    for i in 3 downto 0 loop
        led_input <= (others => NOT ACTIVE_VALUE);
        led_input(i) <= ACTIVE_VALUE;
        wait for clk_period;
    end loop;
    --for i in 0 to 15 loop
    --    led_input <= std_logic_vector(to_unsigned(i, NUM_LEDS));
    --    wait for clk_period;
    --end loop;
    --for i in 15 downto 0 loop
    --    led_input <= std_logic_vector(to_unsigned(i, NUM_LEDS));
    --    wait for clk_period;
    --end loop;
    wait;
  end process;

end;