library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.vhdl_verification.all; entity tb_keypad_emu is end tb_keypad_emu; architecture behavior of tb_keypad_emu is -- DUT parameters constant VERBOSE : boolean := true; -- DUT signals signal keypad_rows : std_logic_vector(3 downto 0); signal keypad_columns : std_logic_vector(3 downto 0); signal pressed_keys : std_logic_vector(15 downto 0); -- Clock period and signal definition -- (we don't actually have a clock in this testbench, but it's nice to have -- some time magnitude, to wait for multiples of it) constant clk_period : time := 10 ns; signal clk : std_logic := '0'; -- Simulation control constant MAX_CYCLES : integer := 64; signal num_cycles : integer := 0; begin -- Instantiate the Unit Under Test (UUT) uut : keypad_emu generic map ( VERBOSE => VERBOSE ) port map ( keypad_rows => keypad_rows, keypad_columns => keypad_columns, pressed_keys => pressed_keys ); -- To stop the simulation without a failure message, -- stop the clock when we reach the desired number of cycles clk_process : process begin if(num_cycles < MAX_CYCLES) then clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; num_cycles <= num_cycles + 1; else report "Ending simulation"; wait; end if; end process; -- Stimulus process -- -- Let's test this thing by sequentially pressing all keys! stim_proc : process begin wait for clk_period; pressed_keys <= (others => '0'); wait for clk_period; for i in 0 to 15 loop pressed_keys <= (others => '0'); pressed_keys(i) <= '1'; wait for clk_period; for j in 0 to 3 loop keypad_columns <= (others => '1'); keypad_columns(j) <= '0'; wait for clk_period; --report "keypad_columns: " & slv2string(keypad_rows); --report "keypad_rows: " & slv2string(keypad_rows); for k in 0 to 3 loop if keypad_rows(k) = '0' then report "Key pressed detected at column " & integer'image(j) & ", row " & integer'image(k); end if; end loop; end loop; end loop; pressed_keys <= (others => '0'); wait; end process; end;