library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_verification.all;

entity tb_datawrite is
  generic (INVALID_DATA : datagen_invalid_data := unknown;
           STIMULI_FILE : string := "../test/datagen_test.txt");
end tb_datawrite;

architecture behavior of tb_datawrite is

  -- Make DATA_WIDTH a testbench-level constant so we can use it in signal declarations
  constant DATA_WIDTH : integer := 1;

  --Inputs
  signal clk    : std_logic := '0';
  signal data   : std_logic_vector(DATA_WIDTH-1 downto 0);
  signal valid  : std_logic;
  signal endsim : std_logic;

  -- Clock period definitions
  constant clk_period : time := 10 ns;
  
begin

  -- Instantiate the Unit Under Test (UUT)
  uut : datawrite
    generic map (
      SIMULATION_LABEL => "datawrite",
      DEBUG            => false,
      VERBOSE          => false,
      OUTPUT_FILE      => "./datawrite_test.log",
      OUTPUT_NIBBLES   => 2,
      DATA_WIDTH       => DATA_WIDTH
      )
    port map (
      clk    => clk,
      data   => data,
      valid  => valid,
      endsim => endsim
      );

  datagen_inst : datagen
    generic map (
      VERBOSE                  => false,
      STIMULI_FILE             => STIMULI_FILE,
      STIMULI_NIBBLES          => 2,
      DATA_WIDTH               => DATA_WIDTH,
      THROUGHPUT               => 2,
      INVALID_DATA             => INVALID_DATA,
      CYCLES_AFTER_LAST_VECTOR => 7
      )
    port map (
      clk       => clk,
      can_write => '1',
      data      => data,
      valid     => valid,
      endsim    => endsim
      );

  -- To stop the simulation without a failure message,
  -- stop the clock when endsim = '1',
  clk_process : process
  begin
    if(endsim /= '1') then
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
    else
      wait;
    end if;
  end process;

end;