library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_verification.all;

entity tb_datagen is
  generic (INVALID_DATA : datagen_invalid_data := unknown;
           STIMULI_FILE : string := "../test/datagen_test.txt");
end tb_datagen;

architecture behavior of tb_datagen is

  -- Make DATA_WIDTH a testbench-level constant so we can use it in signal declarations
  constant DATA_WIDTH : integer := 1;
  constant THROUGHPUT : integer := 5;

  --Inputs
  signal clk : std_logic := '0';

  --Outputs
  signal data   : std_logic_vector(DATA_WIDTH-1 downto 0);
  signal valid  : std_logic;
  signal endsim : std_logic;

  -- Simulation control
  shared variable datacount : integer := 0;

  -- Expected data. Initialized to the same values as the datagen_test.txt file
  type expected_t is array(0 to 9) of std_logic_vector(7 downto 0);
  signal expected : expected_t :=
    (x"A1", x"B2", x"C3", x"D4", x"E5", x"F6", x"37", x"28", x"19", x"4A");

  -- Clock period definitions
  constant clk_period : time := 10 ns;

begin

  uut : datagen
    generic map (
      VERBOSE                  => false,
      STIMULI_FILE             => STIMULI_FILE,
      STIMULI_NIBBLES          => 2,
      DATA_WIDTH               => DATA_WIDTH,
      THROUGHPUT               => THROUGHPUT,
      INVALID_DATA             => INVALID_DATA,
      CYCLES_AFTER_LAST_VECTOR => 7
      )
    port map (
      clk       => clk,
      can_write => '1',
      data      => data,
      valid     => valid,
      endsim    => endsim
      );

  throughputchecker_inst : throughputchecker
    generic map (
      SIMULATION_LABEL => "datagen",
      THROUGHPUT       => THROUGHPUT
      )
    port map (
      clk    => clk,
      valid  => valid,
      endsim => endsim
      );

  -- To stop the simulation without a failure message,
  -- stop the clock when endsim = '1',
  clk_process : process
  begin
    if(endsim /= '1') then
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
    else
      if (datacount = 80) then
        report "Test completed successfully: datacount: " & integer'image(datacount);
      else
        report "Test completed, but data missing: datacount: " & integer'image(datacount);
      end if;

      wait;

    end if;
  end process;

  -- Check output serialized data is correct.
  -- Since we don't have yet datacompare, use assertions.
  monitor : process(clk)
  begin
    if falling_edge(clk) then
      if valid = '1' then
        if data(0) = expected(datacount/8)(datacount mod 8) then
          --report "Data OK";
        else
          report "Data ERROR" severity failure;
        end if;
        datacount := datacount + 1;
        --report "datacount: " & integer'image(datacount);
      end if;
    end if;
  end process;

end;