vhdl-verification

Introduction

vhdl-verification is a VHDL package to ease testing of HDL entities.

The package provides entities to make generation of testbenches easier:

• clkmanager: Manages clock and reset
• datagen: Generates circuit stimuli from a file
• datacompare: Compares circuit output with a file and reports errors
• datawrite: Writes circuit output to a file
• throughputchecker: Checks that circuit complies with a specific output data rate
• led_emu: Simple emulation of on-board leds
• uart_emu: Emulates an uart_receiver
• keypad_emu: Emulates the Digilent 16-button PMOD Keypad

Instructions

1. Download the files from: woden.us.es/docs/vhdl-verification-files
2. To use the package, just add the files to your project. You need to include:
   • The vhdl_verification.vhd header file
   • The txt_util.vhd header file
   • The files that correspond to the entities you want to use (you don't need to include the entities that you will not be using!)
3. In your testbench, instead of redeclaring the components, just include the vhdl_verification package with the sentence:

   use work.vhdl_verification.all

Author

The first entities for this package were developed by Hipolito Guzman-Miranda for the EDELWEISS project. Along the years, some other functionalities and entities have been added.

Educational use is allowed.

Acknowledgement

Special credit to Stephan Doll for creating the txt_util package, which this package uses.