sistema_completo Project Status
Project File: generador_clave_completo_aleatorio.xise Parser Errors: No Errors
Module Name: sistema_completo Implementation State: Synthesized
Target Device: xc3s200-5ft256
  • Errors:
 
Product Version:ISE 13.1
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentlun 1. sep 20:27:56 2014   
Translation ReportOut of Datedom 31. ago 18:46:54 2014000
Map ReportOut of Datedom 31. ago 18:47:16 2014004 Infos (4 new)
Place and Route ReportOut of Datedom 31. ago 18:47:39 2014001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportOut of Datedom 31. ago 18:47:47 2014005 Infos (5 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datedom 12. abr 21:52:06 2015

Date Generated: 04/13/2015 - 16:48:12