sistema_completo Project Status | |||
Project File: | generador_clave_completo_aleatorio.xise | Parser Errors: | No Errors |
Module Name: | sistema_completo | Implementation State: | Synthesized |
Target Device: | xc3s200-5ft256 |
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Product Version: | ISE 13.1 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | lun 1. sep 20:27:56 2014 | ||||
Translation Report | Out of Date | dom 31. ago 18:46:54 2014 | 0 | 0 | 0 | |
Map Report | Out of Date | dom 31. ago 18:47:16 2014 | 0 | 0 | 4 Infos (4 new) | |
Place and Route Report | Out of Date | dom 31. ago 18:47:39 2014 | 0 | 0 | 1 Info (1 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | dom 31. ago 18:47:47 2014 | 0 | 0 | 5 Infos (5 new) | |
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | dom 12. abr 21:52:06 2015 |