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-- Company: 
-- Engineer:
--
-- Create Date:   18:18:49 03/29/2020
-- Design Name:   
-- Module Name:   C:/Users/GOn/Xilinx/estimador/tb_interpolador.vhd
-- Project Name:  estimador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: interpolador
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
use work.edc_common.all;
 
ENTITY tb_interpolador IS
END tb_interpolador;


 
ARCHITECTURE behavior OF tb_interpolador IS 
 
    -- Component Declaration for the Unit Under Test (UUT)

constant INIT : complex10 := (re => to_signed(0,10), im => to_signed(0,10));

    COMPONENT interpolador
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         inf : IN  complex10;
         sup : IN  complex10;
         valid : IN  std_logic;
         estim : OUT  complex10;
         estim_valid : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal inf : complex10 := INIT;
	signal sup : complex10 := INIT;
	signal valid : std_logic := '0';

 	--Outputs
   signal estim : complex10;
   signal estim_valid : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: interpolador PORT MAP (
          clk => clk,
          rst => rst,
          inf => inf,
          sup => sup,
          valid => valid,
          estim => estim,
          estim_valid => estim_valid
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		rst <= '1';
		wait for clk_period*1;
		rst <= '0';
      wait for clk_period*10;
		valid <= '1';
		sup.re <= to_signed(500,10);
		sup.im <= to_signed(500,10);
		inf.re <= to_signed(100,10);
		inf.im <= to_signed(100,10);
		 wait for clk_period*20;
		valid <= '0';
      wait;
   end process;

END;