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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:46:38 03/25/2020 
-- Design Name: 
-- Module Name:    interpolador - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.edc_common.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity interpolador is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           inf : in  complex10;
           sup : in  complex10;
           valid : in  STD_LOGIC;
           estim : out  complex10;
           estim_valid : out  STD_LOGIC);
end interpolador;

architecture Behavioral of interpolador is

-- Definicion de 
-- Tipos
type tipo_estado is (reposo, interpola);
-- Seņales
signal i, p_i : signed (4 downto 0);
signal estim_aux_re, estim_aux_im : signed (14 downto 0);
signal p_estim_valid : STD_LOGIC;
signal estado, p_estado : tipo_estado;
-- Constantes

begin

-- Conexion de seņales si fuese necesario

sinc: process (clk, rst)
begin

if (rst = '1') then
	estim.re <= to_signed(0,10);
	estim.im <= to_signed(0,10);
	estim_valid <= '0';
	i<= to_signed(0,5);
	estado<=reposo;
elsif (rising_edge(clk)) then
	i<=p_i;
	estim_valid <= p_estim_valid;
	estado <= p_estado;
	estim.re <= estim_aux_re (13 downto 4);
   estim.im <= estim_aux_im (13 downto 4);
	
end if;
end process;



fsm: process (valid,estado, sup, inf, estim_aux_re, estim_aux_im, i)
begin
p_estado<=estado;

case estado is
	when reposo =>
		p_i <= to_signed(0,5);
		estim_aux_re <= to_signed(0,15);
		estim_aux_im <= to_signed(0,15);
		p_estim_valid <= '0';
		
		if (valid='1') then
			p_estado <= interpola;
			p_i <= to_signed(0,5);
		end if;
	when interpola =>
		p_estim_valid <= '1';
		estim_aux_re <= sup.re*i+inf.re*(12-i);
		estim_aux_im <= sup.im*i+inf.im*(12-i);
				
		p_i<=i+1;		
		if (i=11) then
			p_estado <= reposo;
			p_i <= to_signed(0,5);
		end if;
	end case;
end process;

end Behavioral;